Nvidia GPUs now contain roughly 10-40 RISC-V microcontroller cores per chip, a change that the company says results in over a billion RISC-V cores shipped annually. These cores handle non-shader tasks - video encode/decode, power management, security, and other management functions - replacing Nvidia’s older Falcon microcontrollers that lacked 64-bit addressing, caches, and OS support. After evaluating Arm, Synopsys ARC, MIPS and RISC-V, Nvidia developed three in-house RISC-V designs (NV-RISCV32, NV-RISCV64, NV-RVV) and a reusable “Peregrine” subsystem that adds tightly-coupled memory, cache, DMA and crypto, plus more than twenty proprietary extensions tailored to GPU needs.
The GPU System Processor (GSP) is the most important instance: a multi-core RV64 platform that runs much of the resource manager and firmware - initialization, power and clock control, and VM partitioning - communicating with the host via RPC. Firmware is delivered as signed ELF64 RISC-V binaries with RSA signature blocks; secure boot and RISC-V PMP-based isolation (libOS) prevent tampering and enable vGPU separation while minimizing exposed MMIO. The result leverages an open ISA for flexibility and isolation but remains a tightly controlled, cryptographically locked implementation rather than an open GPU stack.
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