How did Apple Silicon get 50% faster in three years? – Daniel Lemire's blog

This examines how base Apple Silicon chips (M2 2022 → M3 2023 → M4 2024 → M5 2025) improved roughly 50% in single-core performance and about 80% in multi-core performance on Geekbench 6 over three years. The gains are gradual rather than a single leap: single-core scores rose from ~2,401 to ~3,642 and multi-core from ~9,814 to ~17,955. A large part of the single-core improvement is simple frequency: P‑core max clock climbed from 3.5 GHz to 4.6 GHz (≈30% higher). Efficiency core clocks also ticked up (2.4→3.0 GHz), and core counts for E‑cores increased from 4 to 6 in M4/M5, helping multi‑threaded throughput.

Architectural changes also mattered: transistor count increased (about 20B → 28B from M2 to M4), decode width rose from 8→10 instructions per cycle raising IPC, and memory bandwidth moved from 100 GB/s (M2/M3) to 154 GB/s (M5) thanks to faster LPDDR5X. SIMD execution stayed at four 128‑bit NEON units, but M4/M5 added a 512‑bit SME matrix unit for heavier parallel workloads, while competitors like Zen5 offer wider AVX‑512 SIMD. A brief note on M6: chip count goes from 10→12 cores with two new “super” cores and yet higher bandwidth.