The Intel 8087 chip: floating-point addition and subtraction

Intel's 8087 numeric coprocessor dramatically accelerated floating-point math in early PCs by implementing floating-point addition and subtraction in optimized microcode and specialized datapath circuitry. The chip contains a 1648‑instruction microcode ROM and a datapath with a 69‑bit integer adder, a wide shifter, leading‑zero circuitry, and an exponent converter. Internally numbers use an 80‑bit "temporary real" format (1 sign bit, 15‑bit biased exponent with bias 16383, and a 64‑bit significand). Eight stack registers hold 80‑bit values each with tags (zero, valid, special, empty). Temporary registers tmpA/tmpB hold operands; tmpC is a 68‑bit working significand with an extra high bit plus guard, round, and sticky bits for rounding and overflow protection.

Addition and subtraction are implemented as microcoded sequences that first load operands into tmpA/tmpB, handle zero and special cases, then subtract exponents to determine alignment. If necessary operands are swapped (with a sign‑latch toggle when swapping affects the result sign), tmpB is shifted by the difference using CREATE_DENORM, and the sum/difference is computed by the adder. The adder and shifter each use two micro‑instructions (configure then read result); results go to a sum register and are later normalized, rounded, or negated as required. The microcode covers many edge cases (sign changes, zero, denormals, infinities, NaNs) and relies on dedicated hardware for fast alignment, normalization, and exponent adjustments.