AMD Takes the Lid Off of Next-Gen EPYC 9006 Venice as Zen 6 Comes to Servers

AMD is introducing the EPYC 9006 “Venice” family, bringing Zen 6 to servers with a broad product stack that targets both traditional datacenter and AI use cases. The lineup uses two TSMC 2nm CCD variants - high-performance Zen 6 and dense Zen 6c - delivering up to 96 cores on the performance side and up to 256 cores on dense configurations. CCDs appear to pack 12 cores each and pair 4 MB of L3 cache per core, yielding up to ~384 MB L3 on performance SKUs and up to ~1,024 MB on dense parts. Clock targets are ~5.0 GHz for peak Zen 6 and ~4.1 GHz for dense Zen 6c, shrinking the clock-gap while enlarging the core-count gap versus the prior generation; 3D-stacked L3 returns and a planned AI-focused LPDDR-capable EPYC variant are also part of the roadmap.

The new I/O die (IOD) is a major platform upgrade: Venice supports 16 memory channels, DDR5 RDIMMs to 8,000 MT/s and MRDIMMs to 12,800 MT/s for up to ~1.0 TB/s (RDIMM) or ~1.6 TB/s (MRDIMM) of memory bandwidth. IOD features include PCIe Gen6 and CXL 3.1 support (up to 128 lanes in 1P) and an upgraded xGMI link that provides cache-coherent CPU-GPU memory sharing for tighter GPU coupling. High-end chips use two IODs produced on TSMC 6nm while CCDs use 2nm, a split intended to ease production; AMD has not yet fully detailed how the dual-IOD layout will affect NUMA or other system behaviors.