HBM: High-Bandwidth Mistake

Argues that high-bandwidth memory (HBM) is a technical and economic mistake that will be phased out, because its vertical stacking (TSVs and micro-bumps) creates parasitic bump capacitance that limits pin speed, forces escalating PHY power and thermal costs, and breaks roadmaps. The HBM4 rollout exposed these limits: JEDEC set 8 Gbps/pin while a key customer demanded 11 Gbps/pin, and vendors failed qualification. Custom base-die tweaks help, but only hybrid bonding properly addresses the bump-capacitance impedance. Meanwhile startups are pursuing alternatives: one notable approach replaces HBM with commodity LPDDR5X plus architectural tricks to achieve far higher usable bandwidth without the TSV penalties.

Offers a future path: CXL is only a stopgap because it rides on a suboptimal PCIe PHY, while the scalable solution is disaggregated, optically attached LPDDR memory pools driven by clock-forwarded SerDes directly into optics (demonstrated conceptually at ISSCC 2026). That design promises greater bandwidth per millimeter of beachfront, longer reach, DRAM reuse, higher capacity and thermal headroom, and simpler Rx electronics. Forecasts a steep decline in HBM volume (~90% over 7-10 years) and warns DRAM equities could still rally short term before a deep cyclic drawdown (~70%) later; key indicators to watch are hybrid bonding adoption, optical SerDes commercialization, and LPDDR-centered architectures.