Nagare Labs is developing Z2RAM, a memory technology backed by Playground Global, where former Intel CEO Pat Gelsinger is a partner. Its goal is to ease the “memory wall” that limits AI systems by combining SRAM-like speed with much greater density and simpler production. Founded by Georgia Tech researchers Suman Datta and Shimeng Yu, the startup builds memory cells from oxide-semiconductor transistors and aims to stack them directly onto processor logic through 3D bonding. Unlike DRAM, Z2RAM stores charge in a transistor’s gate capacitance rather than a separate capacitor, making reads non-destructive and potentially faster. Nagare estimates its first version could pack five times as many bits as SRAM in the same area: a 64MB SRAM tile could become a 320MB Z2RAM tile. That could reduce the number of SRAM-heavy AI accelerators needed, though it would not match the capacity of high-bandwidth memory systems.
The technology remains at the laboratory-prototype stage, and its ambitious performance and manufacturing claims are unproven at commercial scale. Nagare has raised $5 million and is seeking a fabrication partner; it hopes to sample working tiles within four years and ship products within a decade. Adoption also depends on solving integration challenges: there is no standard for connecting this kind of 3D-stacked memory to accelerators, so Nagare may need to create an interface or rely on proprietary approaches. Reliability is another concern, since tiny atomic defects in oxide semiconductors can shift transistor behavior enough to corrupt stored data. Gelsinger sees AI’s growing appetite for memory as an opportunity, but the company must overcome demanding validation requirements and a history of memory startups that failed despite promising designs.
Summary generated by AI from the linked article. hn.today is not affiliated with Hacker News or Y Combinator.