vfmaddrnd231pd is documented as a fused multiply-add of packed double-precision floats with per-instruction rounding control: an immediate byte encodes rounding mode, DAZ, FTZ, and exception suppression. That capability would let code override the global x86 rounding state on a single FMA instruction, enabling fine-grained, faster rounding-controlled arithmetic without AVX-512. However, attempts to use it fail in practice: GNU assembler does not recognize the mnemonic, the Intel/Clang/ICC intrinsics named in the manual (_mm_fmaddround_pd, _mm256_fmaddround_pd) are absent, and executing the encoded opcode on a Haswell CPU raises a #UD undefined-instruction fault.
The only SDM evidence is a 2024 manual entry with an unusual opcode form (VEX.DDS.128.66.0F3A.W1 B8 /r /ib) where DDS appears nowhere else, and that same instruction is missing from the 2026 SDM. The combination of unique tables/pseudocode in the older manual, missing assembler/compiler support, the opcode oddity, and runtime undefined behavior leads to the hypothesis that Intel planned a vfmaddrnd group, then removed hardware support late without fully cleaning up documentation. Confirmation from Intel would resolve whether it was a withdrawn design or a documentation error.
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