V100 SXM2 pinout and NVLink reference

This repository is a technical reference kit for designing carrier boards around NVIDIA V100 SXM2 modules, with a longer-term goal of an open-source board. It organizes publicly available pin information and reverse-engineering findings into maps for all 800 contacts across connectors A and B, including signal names, supporting evidence, and electrical-treatment notes. It also provides logical NVLink connection plans for two- and four-GPU systems, specifying connector B pads, directions, lanes, and polarity. The maintainer’s role is primarily to curate and reconcile existing information, rather than claim the original reverse-engineering work.

The kit includes editable KiCad schematics for one, two, or four modules, connector symbols, visual previews, and an offline workbook and PDF sets. The two- and four-GPU schematics show data wiring only; they are not complete NVLink implementations or routed bridge designs. Each V100 also requires an external 156.25 MHz differential NVHS clock on connector B contacts E20 and F20, while a separate 100 MHz PCIe clock goes to connector A contacts E7 and F7. The material is explicitly a pre-release reference, not a hardware-qualified design: power, control, and clock circuits are absent, and manufacturing outputs and validation remain future work. Reuse is permitted under CERN-OHL-W-2.0 for original hardware contributions and CC BY-SA 4.0 for documentation, with attribution and applicable sharing obligations.