This explains why emulating x86’s Total Store Order (TSO) on ARM’s weaker memory model is hard and expensive. x86-TSO gives programmers a simple, strong guarantee: stores become coherently visible to other processors in program order. ARM’s relaxed model originally required costly full barriers, so emulators mapped x86 loads to ARM load-acquire and stores to store-release, which is correct but much stricter than necessary and imposes severe runtime penalties. Microbenchmarks show big slowdowns on several ARM CPUs (notably AmpereOne), while some cores (Cortex-X4/X925) handle the load better. Apple’s silicon implemented a hardware TSO mode so regular loads/stores behave like x86, yielding near-native performance.
Later ARM extensions (FEAT_LRCPC and its follow-ups) add LRCPC loads and related features that match x86 requirements much more efficiently, and switching to them largely removes the earlier overhead on capable hardware. However, practical emulation still grapples with alignment and atomicity quirks - unaligned atomics and split-locks that cross cachelines, uncached memory semantics, and a few edge cases that even LRCPC variants don’t cleanly cover. The best path is hardware support for TSO or richer LRCPC extensions; absent that, emulators must trade correctness, performance, or complexity to approximate x86 behavior.
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