The DRAM interface and the PHY (why a DDR3+ interface must be tuned at boot)

A DDR interface divides into shared command-and-address signals sent from the controller to every chip in a rank, and bidirectional data signals organized into byte lanes. Each lane has its own data pins, mask, and strobe, so routing delays vary lane by lane. DDR uses the source-synchronous strobe DQS to sample data: on writes, the controller centres DQS edges within data bits; on reads, the DRAM sends DQS at bit transitions, so the receiver must delay it. FPGA PHYs implement these timing shifts differently, and some capture reads using DQS while others sample with a fast clock.

DDR3 and DDR4 use fly-by routing for clock, command, and address signals, causing different chips to see the clock at different times. Boot-time training compensates for these and other board and I/O delays. Write leveling adjusts each lane’s DQS until it aligns with the DRAM clock; write-latency calibration corrects whole-clock offsets; and DQ-DQS training centres write data within the strobe window. Read leveling sweeps whole-bit slips and fine input-delay taps, selecting the widest range that returns correct data. A wide passing window indicates more robust timing, while a narrow one can signal electrical or clocking problems. LiteDRAM exposes PHY-specific controls and calibration capabilities through registers, and its BIOS runs the procedures supported by each PHY.