Talking Zen 6 with Mike Clark at AMD In-Depth

AMD architect Mike Clark explains how Zen 6 and Zen 6c diverge from earlier core families: the dense design is no longer merely an area-saving option, but a high-performance core with full L3 allocation and higher IPC. A 32-core implementation provides 128 MB of L3. The higher-frequency core and Zen 6c are intended to run the same software optimizations, while Zen 6c’s lower clock target allows larger queues that can improve IPC and accommodate latency. The interviewer reports that Zen 6c matches AMD’s fastest Zen 5 server CPU in SPECint 2026 despite its lower clock speed.

The discussion details changes across the core. Zen 6 streamlines instruction delivery across Zen 5’s dual-decode front end, reduces integer multipliers from three to two to save area and suit distributed schedulers, and adds two VNNI units for inference and other AI tasks. It also enables four vector loads, sustains 64 bytes per cycle of L2 read bandwidth by preventing prefetches from crowding out demand traffic, and improves branch-misprediction recovery without sacrificing accuracy. Larger queues help cores tolerate increased L3 latency as cache capacity and topology grow. Clark says adding LPDDR5X to the server ecosystem did not substantially change core design, since the system was already provisioned for memory bandwidth.