Show HN: Esp32sim – Run ESP32 firmware in the browser

This is an open-source, Rust-written emulator that runs real ESP32-family firmware instruction-for-instruction, including the mask ROM, second-stage bootloader and unmodified application images. It models multiple Espressif SoCs across both CPU families: Xtensa (classic ESP32 and ESP32‑S3, including dual LX cores) and RISC‑V (ESP32‑C3 and C6). Peripherals are implemented at a functional level (GPIO, UART, timers, SPI flash/PSRAM, I2S, camera, displays like ST7735/ST7789/ST7701S, WS2812, crypto, etc.), and a virtual WiFi AP provides scan, WPA2, DHCP/DNS/NTP and NAT to the host network. The S3 implementation includes an AArch64 JIT for Xtensa and reports high execution rates (~150-240 MInsn/s); the RISC‑V cores run in a fast interpreter. Everything can be built as a WebAssembly module with a browser UI (console, board graphics, audio, camera) so firmware can run in-browser without hardware or cloud accounts. Licensed MIT.

The codebase is modular: emu-core, esp-soc (machine/boards/network), esp-periph (peripheral IP), CPU crates (xtensa-lx7, riscv-rv32), wasm/web front end, CLI and many examples (hello_world, waveshare-cam, wifi-station, a pocket synth demo). Regression golden outputs, decoder checks and JTAG differential tests against real boards are included. Status is mature for the S3 and draft for C3/C6. Build/run instructions and prebuilt demo images are provided; ROM ELFs from ESP‑IDF are required unless using the supplied test ROMs. This lets developers and testers run real ESP32 firmware end-to-end locally or in the browser.