Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5

Qwenputer is an experimental version of Qwen3.5 4B with a deterministic RISC-V processor compiled directly into additional model layers. Rather than using an external tool or sandbox, it runs the CPU during the model’s forward passes. The key is repurposing Gated DeltaNet recurrent-state matrices as addressable RAM: with carefully controlled gates, write strengths and one-hot keys, the system can preserve exact values and read or overwrite specific memory locations. A compiler maps CPU operations onto model components, while generated trace tokens carry addresses, values and execution steps. The resulting 32-bit RV32IM processor passes official RISC-V tests, matches QEMU, and completed an 18-million-instruction run without errors; its arithmetic outputs also showed no mismatches across roughly 230,000 checked positions.

The CPU substantially improves arithmetic performance: on long-integer NUPA problems, accuracy rose from 48.6% for unmodified Qwen to 100%, matching a version equipped with a Python tool. An experimental filesystem built on the same recurrent memory can retain up to 512 files, or about 53,000 tokens, across conversations when its state is saved. The approach has important costs: the checkpoint is 18.8 GB, requires a small driver rather than ordinary generation, and runs slowly because each instruction takes several decoded tokens. Beyond computation and persistent memory, exact control of recurrent state could support safety research, including monitoring hidden reasoning or embedding monitors that the model cannot disable.