Qualcomm's Adreno X2 GPU

Qualcomm’s Adreno X2 GPU, used in the Snapdragon X2 Elite, significantly scales up the Adreno architecture to target laptop iGPU demands: the top X2-90 configuration has eight Shader Processors (four slices) versus six on Adreno X1, and clocks rise from 1.5 to 1.85 GHz. uSPTP units (micro shader+texture blocks) provide 128 FP32 lanes and double-rate FP16, yielding nearly twice the theoretical compute of X1 and capable of beyond-TFLOP FP32 performance in large dispatches (up to ~6 TFLOPS for MADs). Integer throughput is much improved - INT32 adds run at full rate and 32-bit multiplies at half rate - yet FP64 remains unsupported and hardware FMA is absent, so fma() incurs heavy penalties. Reduced register file per uSPTP (128 KB down from 192 KB) and wave64-only mode shape occupancy and the amount of parallelism needed to reach peak throughput.

Memory and rendering architecture retain Adreno idiosyncrasies: tiny 4 KB texture caches that don’t back compute global loads, 128 KB cluster caches feeding a 2 MB L2, and an 8 MB system-level cache (SLC). Measured GPU DRAM bandwidth from a 192-bit LPDDR5X-9523 setup is ~150 GB/s; L2 latency is good but a virtually addressed L2 with a 16K-entry TLB causes sharp latency spikes past ~64 MB working sets. Atomics and cross-core latency are much improved and competitive with recent AMD iGPUs. A 21 MB on-chip Adreno High Performance Memory allows Qualcomm to treat very large tiles (approaching full-screen) for rasterization, containing render targets for QHD+ frames and reducing off-chip traffic.