Playing with the STM32MP2

The STM32MP2 offers a way around the STM32H7’s cumbersome, pin-heavy connection to FPGAs: its 5-Gbps SERDES can support PCIe Gen 1/2 x1, potentially letting firmware access an FPGA over just two differential pairs. Although designed as a Linux-capable application processor, the chip also retains familiar STM32 peripherals and documented cryptographic hardware. The experiment asks whether it can instead behave like a large bare-metal microcontroller: use upstream ARM compilers, run code on its Cortex-A35 and auxiliary Cortex-M33, avoid external DDR and vendor software, and ultimately connect to an FPGA over PCIe.

Initial work brought up the M33 on an STM32MP257 development board, first through JTAG and then from flash using a custom image-header tool and SRAM-based flasher. Booting required careful handling of SRAM aliases: code, stack, and globals use different address mappings but must not overlap physically. The firmware runs in secure mode, so setup includes enabling power monitors, SRAM banks, permissions, clocks, and caches. The A35 proved more involved: it must be separately awakened and released through power, reset, and boot-control registers, and its boot image must reside in flash because the boot ROM runs again when the core starts. A35 initialization also requires assembly for early CPU setup and exception handling. The account establishes the bare-metal foundation, but the supplied material has not yet reached results for PCIe or FPGA communication.