Making a VGA Driver in SystemVerilog

A practical walkthrough of building a VGA driver in SystemVerilog focused on CRT-era timing, FPGA implementation, and image rendering. It explains VGA fundamentals (CRT scanning, HSync/VSync) and targets a ~25.175 MHz pixel clock derived from a 50 MHz DE10‑Lite board clock via a simple clock-divider toggle. Key timing specifics are given: 640 × 480 visible pixels, horizontal total 800 clocks, vertical total 525 lines, and visible windows (horizontal counts ~35-784, vertical 33-520). The design uses parameterized counters to generate enable windows and sync pulses, and a small color-expansion mux to map limited board switches into 4‑bit per channel outputs (00→0000, 01→0101, 10→1010, 11→1111).

Implementation covers simulation, hardware bring‑up, and adding images from ROM. A toolchain step converts images into memory initialization files (rewritten in Go), and the image is displayed at an offset using the horizontal/vertical counters as pixel indices. Transparency support was explored: a boolean alpha test, a bit‑shift approximation for cheap compositing, and finally accurate alpha blending using real multiplication despite gate cost. The project required extensive timing debugging but successfully lights a VGA monitor and renders a composited sprite (Asterix) on the FPGA.