How OpenAI Used Its Own LLMs to Design Its Jalapeño Chip

OpenAI unveiled Jalapeño, its debut AI accelerator, claiming up to 13.4 petaflops of 4-bit compute paired with 232 GB of HBM4 at 15.4 TB/s and benchmarked end-to-end latency reductions up to 3.6× versus Nvidia’s GB300 while using less power. The project moved from first architecture concept to first silicon in under 20 months, with nine months between the first RTL and tape-out, and an average design team of under 100 people. Broadcom partnered on physical implementation, taking responsibility for backend physical design while OpenAI led system architecture, inference accelerator, memory hierarchy, and networking. Jalapeño is intended for large-scale deployment in 2,048-chip pods.

Large language models were central to accelerating front-end design and software optimization. OpenAI integrated LLMs with a high-level synthesis flow based on XLS (DSLX/C++ → Verilog), allowing fast iteration; internal models progressed from o3 to precursors of GPT-6 Astra that can work directly in Verilog and interact with design tools. Using AI to tune software, internal benchmarks rose from 0.31% to 88.94% of theoretical limits in roughly 40 hours. AI-guided physical optimization delivered a reported 10% area reduction for matrix-multiply units, while Broadcom completed backend work. OpenAI calls the models “superpowers” for engineers and intends to fold lessons into future commercial LLMs to further shorten chip design cycles.