European Processor Initiative Concluded

The European Processor Initiative concluded its SGA2 phase after a four-year program with a final review in July 2026, presenting tangible hardware and software results aimed at strengthening Europe’s technological sovereignty. A landmark was the Rhea1 silicon demonstration: first silicon booted a standard Linux distribution with high-bandwidth memory and hardware performance counters, ran HPL and STREAM, and showed a complete HPC software ecosystem ready for exascale workloads. SiPearl’s Rhea1 - presented as an 80-core, highly complex European CPU - is slated to power the JUPITER exascale system, with Rhea2 targeting the next machine, signaling a transition from research to deployable processor products and a recognized European HPC brand.

The program also proved its RISC-V accelerator roadmap with five live demos that moved designs from IP blocks to full-stack platforms. Demo highlights: a VEC-based HPC cluster (out-of-order RISC-V core by Semidynamics, BSC vector unit) running Mini-Fall3D across OpenMP+MPI on MEEP FPGAs and profiled with PAPI/Extrae-Paraver; EPAC 1.5 taped-out chip acting as a PCIe RISC-V accelerator alongside an Arm host using a single combined binary and DMA; Kalray’s KV4-1 showing ~16% FFT performance gains via ISA and microarchitecture co-design; Menta’s Origami EDA achieving ~9× placement speedup on 8 threads for large eFPGAs; and DenseMem’s ZeroPoint compression cutting memory traffic on EPAC 1.5. Partners will publish results and hand momentum to follow-on initiatives (EUPEX, EUPILOT, DARE) to further develop IP and operational systems under EuroHPC/JU funding.