Chip-hex:cost-benefit, energy efficiency and hexagonal

This repository presents an experimental 16-core processor architecture that tests whether a balanced multicore design with a hexagonal network-on-chip can improve performance-per-watt and performance-per-cost. The baseline specification uses 16 homogeneous 64-bit in-order cores targeting a nominal 3 GHz with configurable frequency control, 16 KiB L1 instruction and data caches (14 KiB alternatives under study), and a 2 MiB distributed L2. The design intentionally excludes specialized accelerators and emphasizes simplicity, energy-aware operation, and a hexagonal local-neighborhood interconnect to reduce communication overhead. Key design principles include balanced core complexity, cache and memory optimization, clock and power management features such as clock gating and idle states, and cost-conscious hardware feature selection.

Current work is pre-silicon and driven by a Python-based simulator that evaluates the hexagonal topology, cache-capacity trade-offs, configurable clocking, and synthetic-workload throughput and energy estimates. Reported results are simulation estimates only; no fabricated silicon, verified FPGA implementation, or validated synthesis-derived area/timing/power numbers exist yet. The roadmap covers refining the spec, defining an ISA and binary encoding, implementing a core in SystemVerilog, building the NoC and coherence system, and pursuing FPGA/ASIC prototyping. The repository supports reproducible experimentation, welcomes contributions and criticism, and includes licensing information for reuse.