Building an Order RISC-V CPU from scratch

Specula is a from-scratch, 32-bit RISC-V processor written in Bluespec SystemVerilog, built as a hands-on exploration of out-of-order execution. Its design narrowed from an initial plan for a dual-issue core to a single-issue, speculative processor that can execute independent instructions while others wait on long operations. Register renaming removes false dependencies, while a reorder buffer ensures instructions update architectural state in program order. The project later expanded toward running xv6, adding privileged modes, control and status registers, trap handling, Sv32 virtual memory, and system devices including UART, PLIC, and VirtIO storage. It was also taken through Vivado synthesis for an Artix-7 FPGA.

The frontend translates virtual addresses, expands compressed instructions, and predicts branches using a gshare predictor with a 64-entry pattern table, a six-bit history register, and a 16-entry branch target buffer; only one control-flow instruction may remain unresolved at a time. In the backend, renamed instructions enter an eight-entry reservation station or an eight-entry memory queue, and all are tracked by a 32-entry reorder buffer. A 64-register physical file and free list support renaming. The scheduler issues the lowest-index ready arithmetic or branch instruction, not necessarily the oldest. Execution uses an ALU, a DSP-based multiplier, and a 32-cycle iterative divider. Loads wait until older stores have known addresses, avoiding speculative memory-dependence prediction. The project explains how these mechanisms fit together and reflects the author’s learning through implementing and testing a complex processor design.