AMD's Zen 6 Family: Feeding the Beast

AMD’s Zen 6 is an evolutionary redesign of Zen 5, with substantial changes to parts of the core. Its branch predictor is similarly accurate but recovers from mispredictions faster, and a single thread can now use both instruction-decode clusters. Integer execution improves for simple operations and NOP handling, though AMD removes one of three integer multiply units. Floating-point capacity is unchanged, while VNNI throughput doubles and 256-bit vector loads can reach the same 128 bytes per cycle as 512-bit loads. Zen 6 also raises L2 read bandwidth to 64 bytes per cycle. The biggest family-level shift is that Zen 6c has larger out-of-order structures - including its reorder buffer, register file, schedulers, and load queue - giving it more capacity to keep work in flight and cope with memory delays.

The two designs appear tailored for different priorities: Zen 6 for higher clock speeds, Zen 6c for dense, latency-tolerant workloads. Zen 6’s 12-core chip has 48 MB of L3, while Zen 6c’s 32-core chip has 128 MB; the larger design has higher L3 latency, but its cache can reduce trips to main memory. In SPEC CPU 2026, the higher-clocked Zen 6 EPYC 9686F leads the Zen 6c EPYC 9996 by about 18% overall at their tested settings. At a matched 4.1 GHz, however, Zen 6c leads by roughly 6.7% in integer performance and 4% in floating point, aided by its larger cache. Core-bound tests look similar between them, while memory- and code-heavy workloads expose differences in cache capacity and latency.