Accurate Models of AMD Matrix Cores

GPUs’ matrix multipliers deviate from IEEE 754 in ways that vary across vendors and even across generations from the same vendor, affecting accumulator width, rounding rules, normalization points, intermediate underflow/overflow logic, subnormal handling, and special-input treatment. Because those implementation details are undocumented and differ between architectures, software controls cannot guarantee reproducibility across devices. To tackle this, the authors reverse-engineer and precisely characterize matrix-core numerics on three AMD microarchitectures - CDNA 1, CDNA 2, and CDNA 3 (MI100, MI210/250, MI300A/300X). They construct targeted test vectors for every supported input format and justify how each vector isolates a specific numerical feature, enabling deterministic identification of hardware behaviors that matter for correctness and portability.

Using those experiments, they implement MATLAB models that replicate each architecture’s matrix-multiplier pipeline and then validate them to bit-level fidelity against hardware with an iterative loop of randomized testing and test-refinement, achieving agreement over 10 million random input sets. The validated models expose concrete differences in accumulator precision, rounding and normalization thresholds, and special-case handling, and are applied in two demonstration workloads to quantify application-level accuracy gaps between AMD matrix cores and NVIDIA tensor cores. The result is a set of reproducible, experiment-ready models that let researchers predict and analyze device-specific numerical behavior otherwise hidden by vendor opacity.